Do we have any changes on the CPU feature flags that /proc/cpuinfo and lscpu show after applying the microcode update containing the TSX deprecation?

Environment

• Red Hat Enterprise Linux 7 All
• Red Hat Enterprise Linux 8 All

Issue

• Do we have any changes on the CPU feature flags shown in the outputs from /proc/cpuinfo or lscpu after applying the microcode update IPU 2021.1 containing the TSX deprecation?

flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb invpcid_single pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm mpx rdseed adx smap clflushopt intel_pt xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp md_clear flush_l1d

Resolution

• We would recommend that you take the info in this doc into consideration upon the OSP migration.

• According to the whitepaper provided from Intel namely Content from www.intel.com is not included."Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory Ordering Issue (Revision 1.4): TSX Disable Update", the TSX deprecation just turns on bit 11 on CPUID.07H.0H.EDX (RTM_ALWAYS_ABORT) to force RTM abort. CPUID.07H.0H.EBX[11] for RTM detection and CPUID.07H.0H.EBX[4] for HLE detection continue to be set.

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A

TABLES

Table 3-8. Information Returned by CPUID Instruction

Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 1:

Basic Architecture

CHAPTER 16 PROGRAMMING WITH INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS

16.3.1.1 Detection of HLE Support

A processor supports HLE execution if CPUID.07H.EBX.HLE [bit 4] = 1. However, an application can use the HLE
prefixes (XACQUIRE and XRELEASE) without checking whether the processor supports HLE. Processors without
HLE support ignore these prefixes and will execute the code without entering transactional execution.

16.3.1.2 Detection of RTM Support

A processor supports RTM execution if CPUID.07H.EBX.RTM [bit 11] = 1. An application must check if the processor
supports RTM before it uses the RTM instructions (XBEGIN, XEND, XABORT). These instructions will generate a
#UD exception when used on a processor that does not support RTM.

• This means that RTM and HLE are detected and stored in x86_capability array in get_cpu_cap() even after the TSX deprecation having been applied.

void get_cpu_cap(struct cpuinfo_x86 *c)
{
        u32 eax, ebx, ecx, edx; 

        /* Intel-defined flags: level 0x00000001 */
        if (c->cpuid_level >= 0x00000001) {
                cpuid(0x00000001, &eax, &ebx, &ecx, &edx);

                c->x86_capability[CPUID_1_ECX] = ecx; 
                c->x86_capability[CPUID_1_EDX] = edx; 
        }

        /* Additional Intel-defined flags: level 0x00000007 */
        if (c->cpuid_level >= 0x00000007) {
                cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); <<------------ we run __cpuid(7, ebx, ecx, edx) here.

                c->x86_capability[CPUID_7_0_EBX] = ebx; <<------------ and then stores the return value in ebx to the 10th
                                                                        element (the array index: 9) of ->x86_capability.
                c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
                c->x86_capability[CPUID_7_ECX] = ecx; 
                c->x86_capability[CPUID_7_EDX] = edx; 
        }

• Therefore /proc/cpuinfo and lscpu still show both 'rtm' and 'hle' after applying the TSX deprecation that is contained in the microcode update IPU 2021.1

Root Cause

• TSX is enabled by default in rhel7 all, rhel8.0, rhel8.1, and rhel8.2
• rhel8.3 has the change with which TSX is disabled by default.

	commit 51549ab70ad3500707e912f460e5ebb075f0133e
	Author: Josh Poimboeuf <jpoimboe@redhat.com>
	Date:   Wed Jun 10 03:40:04 2020 -0400

		[redhat] redhat/configs: Change Intel TSX default to off
		

• Therefore the CPU feature flags that /proc/cpuinfo and lscpu shows would be:

• Also we have one BZ for rhel8.6 to backport the patch from upstream 5efc6fa9044c to clear not only 'rtm' but also 'hle' in case of tsx=off

commit 5efc6fa9044c3356d6046c6e1da6d02572dbed6b
Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date:   Fri Jan 10 14:50:54 2020 -0800

    x86/cpu: Update cached HLE state on write to TSX_CTRL_CPUID_CLEAR
    
    /proc/cpuinfo currently reports Hardware Lock Elision (HLE) feature to
    be present on boot cpu even if it was disabled during the bootup. This
    is because cpuinfo_x86->x86_capability HLE bit is not updated after TSX
    state is changed via the new MSR IA32_TSX_CTRL.
    
    Update the cached HLE bit also since it is expected to change after an
    update to CPUID_CLEAR bit in MSR IA32_TSX_CTRL.
    
    Fixes: 95c5824f75f3 ("x86/cpu: Add a "tsx=" cmdline option with TSX disabled by default")
    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Tested-by: Neelima Krishnan <neelima.krishnan@intel.com>
    Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
    Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
    Cc: stable@vger.kernel.org
    Link: https://lore.kernel.org/r/2529b99546294c893dfa1c89e2b3e46da3369a59.1578685425.git.pawan.kumar.gupta@linux.intel.com

• The BZ for rhel8.6:
  This content is not included.BZ#1994421 – HLE feature is still visible

• The BZ for rhel7.9.z:
  This content is not included.BZ#1994233 – HLE feature is still visible even if tsx is off

• The BZ for rhel7.9.z mentioned just right above was CLOSED_WONTFIX on September 1st, 2021 because the bug didn't meet the inclusion criteria for rhel7.9.z.

• Please keep in mind that you will have a change on the feature flags on rhel8.6+ containing the patch as shown below:

• Since BZ#1994233 for rhel7.9.z was CLOSED_WONTFIX, we won't have the case that the patch from 5efc6fa9044c is inclued in rhel7.9.z.

CONCLUSION

• To make a long story short, regardless of whether the microcode update for the TSX deprecation is applied or not, the things are going to be:

• Since BZ#1994233 for rhel7.9.z was CLOSED_WONTFIX, we won't have the case that the patch from 5efc6fa9044c is inclued in rhel7.9.z.

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